This invention relates to a technique for fabricating InP semiconductor structures having juxtaposed high and low resistivity regions and, more particularly, to integrated circuits in which buried interconnections are realized using such structures.
Integrated circuits typically include a plurality of devices (e.g., components or circuits) formed in a single semiconductor wafer. The devices may be electrically isolated from one another by a variety of techniques: p-n junction isolation, etched-groove isolation, or oxide channel isolation, for example. Metallization patterns on the surface of the wafer are used to address selected devices or to interconnect them to one another. Generally speaking, however, the interconnection and/or addressing of devices does not involve buried semiconductor channels to achieve these functions.